Storage control system with data management mechanism and method of operation thereof

ABSTRACT

A storage control system, and a method of operation thereof, including: a recycle write queue for providing a recycle write; a host write queue for providing a host write; and a scheduler, coupled to the recycle write queue and the host write queue, for scheduling the recycle write and the host write for writing to a memory device.

TECHNICAL FIELD

The present invention relates generally to a storage control system andmore particularly to a system for data management.

BACKGROUND ART

Data storage, often called storage or memory, refers to computercomponents and recording media that retain digital data. Data storage isa core function and fundamental component of consumer and industrialelectronics, especially devices such as computers, televisions, cellularphones, mobile devices, and digital video cameras.

Recently, forms of long-term storage other than electromechanical harddisks have become feasible for use in computers. NOT-AND (NAND) flash isone form of non-volatile memory used in solid-state storage devices. Thememory cells are arranged in typical row and column fashion withcircuitry for accessing individual cells. The memory transistors ofthose cells are placed to store an analog value that can be interpretedto hold two logical states in the case of Single Level Cell (SLC) ormore than two logical states in the case of Multi Level Cell (MLC).

A flash memory cell is light in weight, occupies very little space, andconsumes less power than electromechanical disk drives. Construction ofa storage system with this type of memory allows for much higherbandwidths and input/output operations per second (IOPS) than typicalelectromechanical disk drives. More importantly, it is especially ruggedand can operate at a much high temperature range. It will withstandwithout adverse effects repeated drops, each of which would destroy atypical electromechanical hard disk drive. A problem exhibited by flashmemory is that it tends to have a limited life in use.

Thus, a need still remains for better data management devices. In viewof the increasing demand for data management devices, it is increasinglycritical that answers be found to these problems. In view of theever-increasing commercial competitive pressures, along with growingconsumer expectations and the diminishing opportunities for meaningfulproduct differentiation in the marketplace, it is critical that answersbe found for these problems. Additionally, the need to reduce costs,improve efficiencies and performance, and meet competitive pressuresadds an even greater urgency to the critical necessity for findinganswers to these problems.

Solutions to these problems have been long sought but prior developmentshave not taught or suggested any solutions and, thus, solutions to theseproblems have long eluded those skilled in the art.

DISCLOSURE OF THE INVENTION

The present invention provides a method of operation of a storagecontrol system, including: receiving a recycle write from a recyclewrite queue; receiving a host write from a host write queue; andscheduling the recycle write and the host write for writing to a memorydevice.

The present invention provides a storage control system, including: arecycle write queue for providing a recycle write; a host write queuefor providing a host write; and a scheduler, coupled to the recyclewrite queue and the host write queue, for scheduling the recycle writeand the host write for writing to a memory device.

Certain embodiments of the invention have other steps or elements inaddition to or in place of those mentioned above. The steps or elementswill become apparent to those skilled in the art from a reading of thefollowing detailed description when taken with reference to theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a storage control system with data management mechanism in anembodiment of the present invention.

FIG. 2 is an exemplary hardware block diagram of the memory controller.

FIG. 3 is a functional block diagram of a scheduler smoothing functionof the memory controller of FIG. 1.

FIG. 4 is an exemplary diagram of the scheduler smoothing function.

FIG. 5 is a first exemplary graph of the recycle ratio.

FIG. 6 is a second exemplary graph of the recycle ratio.

FIG. 7 is a third exemplary graph of the recycle ratio.

FIG. 8 is a control flow of the scheduler smoothing function.

FIG. 9 is a functional block diagram of a moving average smoothingfunction of the scheduler smoothing function of FIG. 3.

FIG. 10 is a functional block diagram of an exponential moving averagesmoothing function of the scheduler smoothing function of FIG. 3.

FIG. 11 is a functional block diagram of a batch smoothing function ofthe scheduler smoothing function of FIG. 3.

FIG. 12 is a flow chart of a method of operation of a storage controlsystem in a further embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

The following embodiments are described in sufficient detail to enablethose skilled in the art to make and use the invention. It is to beunderstood that other embodiments would be evident based on the presentdisclosure, and that system, process, or mechanical changes may be madewithout departing from the scope of the present invention.

In the following description, numerous specific details are given toprovide a thorough understanding of the invention. However, it will beapparent that the invention may be practiced without these specificdetails. In order to avoid obscuring the present invention, somewell-known circuits, system configurations, and process steps are notdisclosed in detail.

The drawings showing embodiments of the system are semi-diagrammatic andnot to scale and, particularly, some of the dimensions are for theclarity of presentation and are shown exaggerated in the drawing FIGs.

Where multiple embodiments are disclosed and described having somefeatures in common, for clarity and ease of illustration, description,and comprehension thereof, similar and like features one to another willordinarily be described with similar reference numerals. The embodimentshave been numbered first embodiment, second embodiment, etc. as a matterof descriptive convenience and are not intended to have any othersignificance or provide limitations for the present invention.

The term “module” referred to herein can include software, hardware, ora combination thereof in the present invention in accordance with thecontext in which the term is used. For example, the software can bemachine code, firmware, embedded code, and application software. Alsofor example, the hardware can be circuitry, processor, computer,integrated circuit, integrated circuit cores, a microelectromechanicalsystem (MEMS), passive devices, environmental sensors includingtemperature sensors, or a combination thereof.

Referring now to FIG. 1, therein is shown a storage control system 100with data management mechanism in an embodiment of the presentinvention. The storage control system 100 includes a memory sub-system102 having a memory controller 104 and a memory array 106. The storagecontrol system 100 includes a host system 108 communicating with thememory sub-system 102.

The memory controller 104 provides data control and management of thememory array 106. The memory controller 104 interfaces with the hostsystem 108 and controls the memory array 106 to transfer data betweenthe host system 108 and the memory array 106.

The memory array 106 includes an array of memory devices 110 includingflash memory devices or non-volatile memory devices. The memory array106 can include pages of data or information. The host system 108 canrequest the memory controller 104 for reading, writing, and deletingdata from or to a logical address space of a storage device or thememory sub-system 102 that includes the memory array 106.

Referring now to FIG. 2, therein is shown an exemplary hardware blockdiagram of the memory controller 104. The memory controller 104 caninclude a control unit 202, a storage unit 204, a memory interface unit206, and a host interface unit 208. The control unit 202 can include acontrol interface 210. The control unit 202 can execute software 212stored in the storage unit 204 to provide the intelligence of the memorycontroller 104.

The control unit 202 can be implemented in a number of differentmanners. For example, the control unit 202 can be a processor, anembedded processor, a microprocessor, a hardware control logic, ahardware finite state machine (FSM), a digital signal processor (DSP),or a combination thereof.

The control interface 210 can be used for communication between thecontrol unit 202 and other functional units in the memory controller104. The control interface 210 can also be used for communication thatis external to the memory controller 104.

The control interface 210 can receive information from the otherfunctional units or from external sources, or can transmit informationto the other functional units or to external destinations. The externalsources and the external destinations refer to sources and destinationsexternal to the memory controller 104.

The control interface 210 can be implemented in different ways and caninclude different implementations depending on which functional units orexternal units are being interfaced with the control interface 210. Forexample, the control interface 210 can be implemented with a dedicatedhardware including an application-specific integrated circuit (ASIC), aconfigurable hardware including a field-programmable gate array (FPGA),a discrete electronic hardware, or a combination thereof.

The storage unit 204 can include both hardware and the software 212. Forexample, the software 212 can include control firmware. The storage unit204 can include a volatile memory, a nonvolatile memory, an internalmemory, an external memory, or a combination thereof. For example, thestorage unit 204 can be a nonvolatile storage such as non-volatilerandom access memory (NVRAM), Flash memory, disk storage, or a volatilestorage such as static random access memory (SRAM).

The storage unit 204 can include a storage interface 214. The storageinterface 214 can also be used for communication that is external to thememory controller 104. The storage interface 214 can receive informationfrom the other functional units or from external sources, or cantransmit information to the other functional units or to externaldestinations. The external sources and the external destinations referto sources and destinations external to the memory controller 104.

The storage interface 214 can include different implementationsdepending on which functional units or external units are beinginterfaced with the storage unit 204. The storage interface 214 can beimplemented with technologies and techniques similar to theimplementation of the control interface 210.

The memory interface unit 206 can enable external communication to andfrom the memory controller 104. For example, the memory interface unit206 can permit the memory controller 104 to communicate with the memoryarray 106 of FIG. 1.

The memory interface unit 206 can include a memory interface 216. Thememory interface 216 can be used for communication between the memoryinterface unit 206 and other functional units in the memory controller104. The memory interface 216 can receive information from the otherfunctional units or can transmit information to the other functionalunits.

The memory interface 216 can include different implementations dependingon which functional units are being interfaced with the memory interfaceunit 206. The memory interface 216 can be implemented with technologiesand techniques similar to the implementation of the control interface210.

The host interface unit 208 allows the host system 108 of FIG. 1 tointerface and interact with the memory controller 104. The hostinterface unit 208 can include a host interface 218 to providecommunication mechanism between the host interface unit 208 and the hostsystem 108.

The control unit 202 can operate the host interface unit 208 to sendcontrol or status information generated by the memory controller 104 tothe host system 108. The control unit 202 can also execute the software212 for the other functions of the memory controller 104. The controlunit 202 can further execute the software 212 for interaction with thememory array 106 via the memory interface unit 206.

The functional units in the memory controller 104 can work individuallyand independently of the other functional units. For illustrativepurposes, the memory controller 104 is described by operation of thememory controller 104 with the host system 108 and the memory array 106.It is understood that the memory controller 104, the host system 108,and the memory array 106 can operate any of the modules and functions ofthe memory controller 104.

Referring now to FIG. 3, therein is shown a functional block diagram ofa scheduler smoothing function 302 of the memory controller 104 ofFIG. 1. Generally, the scheduler smoothing function 302 can be employedin the storage control system 100 of FIG. 1 and more specifically in thememory controller 104. However, it is to be understood that thepreceding examples are not meant to be limiting and the schedulersmoothing function 302 can be employed in any type of system thatrequires data management.

Generally, the scheduler smoothing function 302 can include a host writequeue 304, a recycle write queue 306, a scheduler 308, and a memorywrite operation queue 310. The memory write operation queue 310 caninterleave host and recycle writes to the memory devices 110 of FIG. 1including flash devices. In at least one embodiment, the scheduler 308can receive inputs from one or both of the host write queue 304 and therecycle write queue 306 to create an output write sequence that isdelivered and implemented by the memory write operation queue 310 withinthe storage control system 100.

Per the embodiments described herein, the term “host write” is definedherein as a physical write of new data from the host system 108 of FIG.1 to write to a particular logical address range. Per the embodimentsdescribed herein, the term “recycle write” is defined herein as aphysical write of data that the drive is moving due to recycling. Perthe embodiments described herein, the term “scheduler” is defined hereinas a module in the memory controller 104 including a solid-state drive(SSD) responsible for determining which operations to perform next tothe memory devices 110.

In general, the host write queue 304 can perform operations such asreads and writes submitted by a system external to the memory sub-system102 of FIG. 1. The recycle write queue 306 can perform operationsincluding recycle writes 312, such as reads, writes, and erases that thestorage control system 100 must perform in order to free up space forhost writes 314 and to maintain data integrity.

During operation of the scheduler smoothing function 302, the host writequeue 304 can send a host write request to the scheduler smoothingfunction 302. The host write request can be associated with a physicalwrite of new data from the host system 108 to write to a particularlogical address range. Per the embodiments described herein, the term“physical write” is defined herein as a write that goes to an endstorage element of a system of memory, such as a volatile memory or anon-volatile memory including a NAND flash device.

During operation of the scheduler smoothing function 302, the recyclewrite queue 306 can also send a recycle write request to the schedulersmoothing function 302. The recycle write request can be associated witha physical write of data that the storage control system 100 is movingdue to recycling. Per the embodiments described herein, the term“recycling” is defined herein as moving data from one page to anotherpage, for purposes of either freeing up erase blocks to write new hostdata or to ensure that data on the erase blocks is preserved. Recyclingcan also be referred to as garbage collection.

Per the embodiments described herein, the term “erase block” is definedherein as a group of pages that is the smallest number of pages that canbe erased at one time. Per the embodiments described herein, the term“page” is defined herein as the smallest group of data bytes that can beread from or written to in an erase block.

It is to be understood that write requests from the host write queue 304and the recycle write queue 306 can include any type of write operationor request, such as competing writes, metadata writes, RAID/paritywrites, etc.

After receiving a number of host write requests and/or recycle writerequests, the scheduler smoothing function 302 can then determine whichwrite operation or sequence of write operations to perform next tooptimize performance of the storage control system 100. By way ofexample and not by way of limitation, the storage control system 100 canbe optimized by providing a steady host performance to the user, aconsistent host command latency period to the user, and/or maintenanceof a desired recycle ratio.

Per the embodiments described herein, the term “recycle ratio” isdefined herein as a number of logical pages that are written forrecycling compared to a total number of data writes. Per the embodimentsdescribed herein, the term “host performance” is defined hereingenerally as how much work the host system 108 achieves when interfacingto the memory controller 104 including the SSD. For example, keymeasurements for the host performance can include throughput, averagelatency, worst-case latency, and latency deviation. The key measurementscan be applied to any combinations of host write and host readdistributions, sizes, and queue depths.

Once the scheduler smoothing function 302 has determined the correctwrite operation or sequence of write operations to perform next, thescheduler smoothing function 302 can then send this instruction to thememory write operation queue 310 for implementation within the memoryarray 106 of FIG. 1.

Functions or operations of the memory controller 104 as described abovecan be implemented in hardware, software, or a combination thereof. Thememory controller 104 can be implemented with the control unit 202 ofFIG. 2, the storage unit 204 of FIG. 2, the memory interface unit 206 ofFIG. 2, the host interface unit 208 of FIG. 2, or a combination thereof.

For example, the host write queue 304 can be implemented with thecontrol unit 202 and the storage unit 204 to store and provide the hostwrites 314. Also for example, the recycle write queue 306 can beimplemented with the control unit 202 and the storage unit 204 to storeand provide the recycle writes 312.

For example, the scheduler 308 can be implemented with the control unit202 to receive inputs from one or both of the host write queue 304 andthe recycle write queue 306 to create an output write sequence that isdelivered and implemented by the memory write operation queue 310. Alsofor example, the memory write operation queue 310 can be implementedwith the control unit 202 and the storage unit 204 to receive sequenceof write operations to perform next from the scheduler 308.

The host write queue 304 and the recycle write queue 306 can be coupledto the scheduler 308. The scheduler 308 can be coupled to the memorywrite operation queue 310.

The storage control system 100 is described with module functions ororder as an example. The modules can be partitioned differently. Forexample, the scheduler 308 and the memory write operation queue 310 canbe combined. Each of the modules can operate individually andindependently of the other modules.

Furthermore, data generated in one module can be used by another modulewithout being directly coupled to each other. The host write queue 304,the recycle write queue 306, the scheduler 308, and the memory writeoperation queue 310 can be implemented as hardware accelerators (notshown) within the control unit 202 or can be implemented as hardwareaccelerators (not shown) in the memory controller 104 or outside of thememory controller 104.

Referring now to FIG. 4, therein is shown an exemplary diagram of thescheduler smoothing function 302. Generally, the scheduler smoothingfunction 302 can include the host write queue 304, the recycle writequeue 306, the scheduler 308, and the memory write operation queue 310.However, in this embodiment, the scheduler smoothing function 302 can betargeted to a particular recycle ratio.

Generally, the memory devices 110 of FIG. 1 are limited by the bandwidthof a heavy write load. In order for the memory devices 110 to displayuniform and/or even performance, the memory devices 110 should maintaina substantially even ratio of the recycle writes 312 and the host writes314. Any deviation from this ratio from second to second can show up inInputs and Outputs per Second (IOPS) and latency measurements. Thisratio can be commonly referred to as a recycle ratio 402 (RR) and can beexpressed as:

$\begin{matrix}{{{Recycle}\mspace{14mu}{Ratio}} = \frac{{recycle}\mspace{14mu}{writes}}{{physical}\mspace{14mu}{data}\mspace{14mu}{writes}}} & (1)\end{matrix}$

Generally, a correlation can exist between a write amplification 404(WA) and the recycle ratio 402 required for a particular value of thewrite amplification 404. This correlation can be expressed as:

$\begin{matrix}{{RR} = {1 - \frac{1}{WA}}} & (2)\end{matrix}$

The recycle ratio 402 can be expressed as a function of the writeamplification 404. Particularly, the recycle ratio 402 can be expressedas one minus a reciprocal of the write amplification 404.

Accordingly, even though the embodiments described herein generallyfocus on the recycle ratio 402, the principles can apply equally well toa method and/or system that utilizes the write amplification 404measurements. Per the embodiments described herein, the term “writeamplification” is defined herein as a ratio of physical writes to amedia compared to the host writes 314 to the memory device 110.

In at least one embodiment, the scheduler smoothing function 302 cantarget a desired value of the recycle ratio 402. For example, if thescheduler smoothing function 302 knows a ratio of the host writes 314that it should perform relative to total writes, it can target thatratio in its scheduling and as a result be as responsive to the hostsystem 108 of FIG. 1 as possible while fulfilling the recycling workthat the memory devices 110 need to continue functioning.

Accordingly, after receiving inputs from the host write queue 304 andthe recycle write queue 306, the scheduler smoothing function 302 canthen organize these inputs pursuant to a predefined value of a targetrecycle ratio 406. Per the embodiments described herein, the term“target recycle ratio” is defined herein as a recycle ratio that ascheduling algorithm is targeting. This is abbreviated as RR_(t).

For example, if the target recycle ratio 406 is 0.75, the schedulersmoothing function 302 can then output an instruction to the memorywrite operation queue 310 indicating that roughly three (3) of everyfour (4) writes should be the recycle writes 312. The target recycleratio 406 of 0.75 is depicted in the memory write operation queue 310,wherein the order in which the scheduler smoothing function 302 candispatch the write operations to the memory devices 110 is shown.However, it is to be understood that the target recycle ratio 406 is notlimited to the preceding exemplary value of 0.75 and the target recycleratio 406 can include any value between and including 0.0 and 1.0.

As such, when the behavior of the host system 108 varies and/or as theneeds of the memory devices 110 change, the target recycle ratio 406 canchange as well. Accordingly, in at least one embodiment of theinvention, if the storage control system 100 of FIG. 1 determines thatthe scheduler smoothing function 302 would benefit from a new value ofthe target recycle ratio 406, the scheduler smoothing function 302 canbe reprogrammed to use the new value of the target recycle ratio 406.

It has been discovered that the scheduler smoothing function 302 permitsenhanced flexibility for the needs of the host system 108 and the memorydevices 110. For example, the scheduler smoothing function 302 permitsthe storage control system 100 to perform the recycle writes 312 whenthere is none of the host writes 314 to schedule. As such, this enhancedflexibility allows the memory devices 110 to catch up or get ahead onthe recycle writes 312 so that it does not have to perform as many lateron if the host system 108 decides to perform more of the host writes314.

It has been discovered that the enhanced flexibility of the schedulersmoothing function 302 also permits the memory devices 110 to perform aburst of the host writes 314 even if the recycle ratio 402 wouldnormally indicate doing more of the recycle writes 312. The schedulersmoothing function 302 of the present embodiments permits a burst of thehost writes 314 because the memory devices 110 can perform additionalrecycle writes later thereby providing better performance to the hostsystem 108 in cases where the host write activity is burst oriented.

Referring now to FIG. 5, therein is shown a first exemplary graph of therecycle ratio 402. Generally, the first exemplary graph plots therecycle ratio 402 on the Y-axis against a spare pool size 502 on theX-axis. Per the embodiments described herein, the term “spare pool” isdefined herein as erased memory that is available to be written to andcan be in units of erase blocks. In at least one embodiment, the firstexemplary graph can be used to determine a value for the target recycleratio 406 of FIG. 4 that the storage control system 100 of FIG. 1 and/orthe scheduler smoothing function 302 of FIGS. 3 and 4 can use.

Generally, the storage control system 100, when under a constant hostworkload, can dynamically determine a steady-state recycle ratio or therecycle ratio 402 from the first exemplary graph. In at least oneembodiment, the steady state recycle ratio or value can be determined byhaving the storage control system 100 sample an available spare poolsize or the spare pool size 502 and assigning a corresponding recycleratio or the recycle ratio 402. As such, the recycle ratio 402 can beset based on a current size of a spare pool or the spare pool size 502.

Accordingly, in at least one embodiment, as the spare pool shrinks insize, the storage control system 100 can increase the recycle ratio 402.Conversely, as the spare pool increases in size, the memory system candecrease the recycle ratio 402. One possible correlation between thespare pool size 502 and the recycle ratio 402 is depicted in FIG. 5.

Generally, the first exemplary graph includes a first region 504 and asecond region 506. The first region 504 can include a substantiallyhorizontal portion of the graph wherein the value of the recycle ratio402 remains substantially constant around a value of one (1) over arange of the spare pool size 502 that varies from zero (0) erase blocksleft to a value deemed “critically low.” The numerical value assigned tothe qualitative term “critically low” can be predetermined or it can beempirically determined.

In at least one embodiment, factors used to empirically determine thevalue can include, but are not limited to, age of the memory devices 110of FIG. 1, recent host performance requirements, latency history, badblock management, etc. In another embodiment, a “critically low” valuecan occur when a number of free erase blocks approaches approximately0.1% of a total number of the erase blocks. In yet another embodiment, a“critically low” value can occur when a number of free or empty eraseblocks is equal to or less than approximately 20 out of the 4,000 eraseblocks on each die or each of the memory devices 110.

The second region 506 can include a substantially linear portion of thegraph with a decreasing slope, wherein the value of the recycle ratio402 decreases from around a value of one (1) to a value of zero (0). Thevalue of the recycle ratio 402 can decrease over a range of the sparepool size 502 that varies from a value deemed “critically low” to avalue corresponding to the “maximum” spare pool size. The numericalvalue assigned to the qualitative term “maximum” can be predetermined orit can be empirically determined.

In at least one embodiment, if the spare pool grows to a maximum size,the memory devices 110 can stop performing recycle operations becausethe recycle ratio 402 can be set to zero. However, it will beappreciated by those skilled in the art that the memory devices 110 neednot totally stop performing recycle operations and can continueperforming background-recycling operations. Generally, the value of thespare pool size 502 between “critically low” and “maximum” can act as abuffer region to help determine the potentially optimal steady statevalue for the recycle ratio 402.

It will be appreciated by those skilled in the art that if the recycleratio 402 is not high enough to maintain a steady state for the storagecontrol system 100, the size of the spare pool or the spare pool size502 can decrease. Accordingly, in response, the first exemplary graph ofthe present embodiments would adjust the recycle ratio 402 to a highervalue. In such cases, one of two things can happen: 1) the recycle ratio402 can be set to a high enough value to be sustainable, or 2) the sparepool can become “critically low” and servicing of host operations cancease.

If the recycle ratio 402 is set to a high enough value to besustainable, the storage control system 100 should reach a steady statein regards to a number of recycle operations that are performed forevery host operation. It will be appreciated by those skilled in the artthat when in this steady state, the spare pool size 502 changes verylittle, if at all.

If the spare pool becomes critically low and servicing of hostoperations ceases, the first exemplary graph can command the storagecontrol system 100 to perform only recycle operations. In such cases,once the spare pool size 502 gets above this critically low mark, therecycle ratio 402 can be set to a value that allows some host operationsto be serviced. It will be appreciated by those skilled in the art thatthis critically low mark should be used only in extreme cases as asafety net to prevent device failure or extended inoperable responses.

Once a steady state for a particular host workload is determined, therecycle ratio 402 and the host performance should be constant. However,when the host changes the workload, a different steady state can berequired by the storage control system 100. For example, if the newworkload requires a higher value of the recycle ratio 402, the sparepool can shrink and the storage control system 100 can adapt byincreasing the recycle ratio 402 until it reaches a new steady state.

Conversely, if the new workload requires a lower value of the recycleratio 402, the spare pool can slowly grow. It will be appreciated bythose skilled in the art that in response to the larger spare pool, therecycle ratio 402 can decrease pursuant to the first exemplary graphthereby permitting more of the host writes 314 of FIG. 3 to beperformed.

As such, a method and/or system have been discovered for dynamicallyadjusting the recycle ratio 402 of the memory devices 110. The dynamicadjustment of the recycle ratio 402 of the present embodiments happensdirectly because of the spare pool shrinking or growing in size, so thememory devices 110 do not have to try to predict the recycle ratio 402that can be needed by the host system 108 of FIG. 1.

It will be appreciated by those skilled in the art that additionalequations and/or curves can be used to translate the spare pool size 502into a target value of the recycle ratio 402. Accordingly, the functionor algorithm used to determine the recycle ratio 402 does not have to belinear in regards to the spare pool size 502. The function may beexponential, logarithmic, mapping, etc.

It will be appreciated by those skilled in the art that if the recycleratio 402 reaches a value of one (1) (e.g., the maximum value), thescheduler smoothing function 302 need not service the host writes 314.

It will also be appreciated by those skilled in the art that the currentembodiments permit the memory devices 110 to perform some recyclingoperations including the recycle writes 312 of FIG. 3 when there are nohost operations including the host writes 314.

Referring now to FIG. 6, therein is shown a second exemplary graph ofthe recycle ratio 402. Generally, the second exemplary graph plots therecycle ratio 402 on the Y-axis against the spare pool size 502 on theX-axis. In at least one embodiment, the second exemplary graph can beused to determine a target value for the recycle ratio 402 that thestorage control system 100 of FIG. 1 and/or the scheduler smoothingfunction 302 of FIGS. 3 and 4 can use. Per this embodiment, the secondexemplary graph can include periods of little change in the recycleratio 402 and periods of larger change in the recycle ratio 402.

The second exemplary graph can include a transition region 602 and astable region 604. The transition region 602 includes a portion of thegraph wherein the recycle ratio 402 experiences a relatively largechange over a relatively small range of the spare pool size 502. In atleast one embodiment, the recycle ratio 402 can change by five percent(5%) or more in the transition region 602.

The stable region 604 marks a portion of the second exemplary graphwherein the recycle ratio 402 remains relatively constant over a rangeof values of the spare pool size 502. By way of example and not by wayof limitation, the spare pool size 502 can change by five percent (5%)or more in the stable region 604, while the recycle ratio 402 can remainrelatively constant over that range. As such, the second exemplary graphpermits a correlation between the recycle ratio 402 and the spare poolsize 502 that can adjust in ranges.

It will be appreciated by those skilled in the art that additionalequations and/or curves can be used to translate the spare pool size 502into the target value of the recycle ratio 402. Accordingly, thefunction or algorithm used to determine the recycle ratio 402 does nothave to be linear in regards to the spare pool size 502. The functioncan be exponential, logarithmic, mapping, etc.

Referring now to FIG. 7, therein is shown a third exemplary graph of therecycle ratio 402. The third exemplary graph can include workloadtransitions. Generally, the third exemplary graph plots the recycleratio 402 on the Y-axis against a time 702 on the X-axis. In at leastone embodiment, the third exemplary graph can depict a transitionalperiod 704 for the recycle ratio 402 that occurs between differentsteady states 706 that the storage control system 100 of FIG. 1 and/orthe scheduler smoothing function 302 of FIGS. 3 and 4 can use.

Generally, when the host system 108 of FIG. 1 changes workloads, therecan be the transitional period 704 when the recycle ratio 402 is higherthan its new steady state. During this time, host performance may not besteady.

A dotted line depicts a transitional period response of the transitionalperiod 704 for the embodiments described herein, wherein hostperformance degradation is minimized. It will be appreciated by thoseskilled in the art that host performance degradation is minimized withthe transitional period response of the dotted line because the changein the recycle ratio 402 is minimized. A dashed line above the dottedline depicts another transitional period response of the transitionalperiod 704 wherein the host experiences greater host performancedegradation due to the larger increase in the recycle ratio 402.

It has been discovered that by using the recycle ratio 402 functionsdescribed herein and/or the spare pool size 502 of FIG. 5 describedherein that the uneven host performance caused by workload transitionsis significantly reduced.

Referring now to FIG. 8, therein is shown a control flow of thescheduler smoothing function 302. The scheduler smoothing function 302can be implemented in the memory controller 104 of FIG. 1 with the hostwrite queue 304 of FIG. 3, the recycle write queue 306 of FIG. 3, thescheduler 308 of FIG. 3, and the memory write operation queue 310 ofFIG. 3. The control flow depicts the scheduler smoothing function 302implemented as a smoothing feedback loop. Generally, the smoothingfeedback loop teaches how to perform the mixing of the host writes 314of FIG. 3 and the recycle writes 312 of FIG. 3 that the schedulersmoothing function 302 implements.

In at least one embodiment, the scheduler smoothing function 302 canimplement the recycle ratio 402 of FIG. 4 by using the smoothingfeedback loop to determine whether the scheduler smoothing function 302needs to schedule one of the host writes 314 or the recycle writes 312next. In such cases, the smoothing feedback loop can track and/ormanipulate a current recycle ratio 802 (RR_(c)) that the schedulersmoothing function 302 has sent out. Per the embodiments describedherein, the term “current recycle ratio” is defined herein as a recycleratio that a scheduling algorithm has been achieving over apredetermined recent history. This is abbreviated as RR_(c).

The smoothing feedback loop can begin with an update RR_(c) module 803.The update RR_(c) module 803 ensures that the smoothing feedback looputilizes the most current recycle ratio or the most current value of therecycle ratio 402 for its algorithm or calculation. In at least oneembodiment, the update RR_(c) module 803 can determine the currentrecycle ratio 802 or a current value of the recycle ratio 402 byutilizing inputs from a schedule host write module 812 and/or a schedulerecycle write module 816. The current value of the recycle ratio 402 ofthe update RR_(c) module 803 can then be fed to a comparison module 804.

In the comparison module 804, the current recycle ratio 802 can becompared to the target recycle ratio 406 (RR). Generally, if the currentrecycle ratio 802 is greater than or equal to the target recycle ratio406, the smoothing feedback loop can choose a first path. If the currentrecycle ratio 802 is less than the target recycle ratio 406, thesmoothing feedback loop can choose a second path.

Accordingly, in at least one embodiment, if the current recycle ratio802 is greater than or equal to the target recycle ratio 406(RR_(c)≥RR_(t)), the smoothing feedback loop can then move to a hostscheduler module 808. Upon receiving an input from the comparison module804, the host scheduler module 808 can determine if there is one of thehost writes 314 to schedule. If there is one of the host writes 314 toschedule, the smoothing feedback loop can then move to the schedule hostwrite module 812. The schedule host write module 812 can then send itsschedule host write request to the update RR_(c) module 803 to be usedin determining the current recycle ratio 802.

If there is none of the host writes 314 to schedule at the hostscheduler module 808, the smoothing feedback loop can then move to arecycle scheduler module 810. If there is one of the recycle writes 312to schedule, the smoothing feedback loop can then move to the schedulerecycle write module 816. The schedule recycle write module 816 can thensend its schedule recycle write request to the update RR_(c) module 803to be used in determining the current recycle ratio 802. If there isnone of the recycle writes 312 to schedule when the smoothing feedbackloop reaches the recycle scheduler module 810, the smoothing feedbackloop can then move back to the comparison module 804.

In another embodiment, if the current recycle ratio 802 is less than thetarget recycle ratio 406 (RR_(c)<RR_(t)) or there is none of the recyclewrites 312 to schedule from the recycle scheduler module 810 when thesmoothing feedback loop reaches the comparison module 804, the smoothingfeedback loop can then move to a host write burst module 814. If thesmoothing feedback loop determines that a host write burst can beperformed at the host write burst module 814, the smoothing feedbackloop can then move to the host scheduler module 808 and can proceed asdescribed above. If the smoothing feedback loop determines that a hostwrite burst cannot be performed at the host write burst module 814, thesmoothing feedback loop can then move to the recycle scheduler module810 and can proceed as described above.

It will be appreciated by those skilled in the art that the smoothingfeedback loop optimizes host performance by keeping the current recycleratio 802 close to the target recycle ratio 406 when a steady stream ofhost activity is observed. By way of example and not by way oflimitation, when the steady stream of the host activity is observed, thecurrent recycle ratio 802 is kept within plus or minus ten percent (10%)of the target recycle ratio 406.

It will be appreciated by those skilled in the art that the smoothingfeedback loop optimizes host performance by allowing the current recycleratio 802 to drop relative to the target recycle ratio 406 for a shortperiod of time when a burst of the host activity is observed. By way ofexample and not by way of limitation, the current recycle ratio 802varies by about ten percent (10%) from the target recycle ratio 406 insuch instances.

It will be appreciated by those skilled in the art that the smoothingfeedback loop optimizes host performance by allowing the current recycleratio 802 to grow or increase relative to the target recycle ratio 406for a period of time when a lull in host activity is observed. By way ofexample and not by way of limitation, the current recycle ratio 802varies by about ten percent (10%) from the target recycle ratio 406 insuch instances.

It has been discovered that such a method and/or system enhances theflexibility of the memory devices 110 of FIG. 1 by allowing thesmoothing feedback loop and/or the scheduler smoothing function 302 tohandle various scenarios and track how far it has deviated from thetarget recycle ratio 406. At the same time, the smoothing feedback loopand/or the scheduler smoothing function 302 are permitted to converge onthe actual value of the target recycle ratio 406 later.

Functions or operations of the memory controller 104 as described abovecan be implemented in hardware, software, or a combination thereof. Thememory controller 104 can be implemented with the control unit 202 ofFIG. 2, the storage unit 204 of FIG. 2, the memory interface unit 206 ofFIG. 2, the host interface unit 208 of FIG. 2, or a combination thereof.

For example, the update RR_(c) module 803 can be implemented with thecontrol unit 202 to ensure that the smoothing feedback loop utilizes themost current value of the recycle ratio 402 and determine the currentvalue of the recycle ratio 402 by utilizing inputs from the schedulehost write module 812 and/or the schedule recycle write module 816. Alsofor example, the comparison module 804 can be implemented with thecontrol unit 202 to compare the current recycle ratio 802 to the targetrecycle ratio 406.

For example, the host scheduler module 808 can be implemented with thecontrol unit 202 to determine if there is one of the host writes 314 toschedule. Also for example, the recycle scheduler module 810 can beimplemented with the control unit 202 to determine if there is one ofthe recycle writes 312 to schedule.

For example, the schedule host write module 812 can be implemented withthe control unit 202 to schedule the host writes 314. Also for example,the host write burst module 814 can be implemented with the control unit202 to determine if a host write burst can be performed. Further, forexample, the schedule recycle write module 816 can be implemented withthe control unit 202 to schedule one of the recycle writes 312.

The update RR_(c) module 803 can be coupled to the comparison module804, the schedule host write module 812, and the schedule recycle writemodule 816. The comparison module 804 can be coupled to the hostscheduler module 808, the recycle scheduler module 810, and the hostwrite burst module 814.

The host scheduler module 808 can be coupled to the recycle schedulermodule 810, the schedule host write module 812, and the host write burstmodule 814. The recycle scheduler module 810 can be coupled to the hostwrite burst module 814 and the schedule recycle write module 816.

The storage control system 100 of FIG. 1 is described with modulefunctions or order as an example. The modules can be partitioneddifferently. For example, the recycle scheduler module 810 and theschedule recycle write module 816 can be combined. Each of the modulescan operate individually and independently of the other modules.

Furthermore, data generated in one module can be used by another modulewithout being directly coupled to each other. The update RR_(c) module803, the comparison module 804, and the host scheduler module 808 can beimplemented as hardware accelerators (not shown) within the control unit202 or can be implemented as hardware accelerators (not shown) in thememory controller 104 or outside of the memory controller 104. Therecycle scheduler module 810, the schedule host write module 812, thehost write burst module 814, and the schedule recycle write module 816can be implemented as hardware accelerators (not shown) within thecontrol unit 202 or can be implemented as hardware accelerators (notshown) in the memory controller 104 or outside of the memory controller104.

Referring now to FIG. 9, therein is shown a functional block diagram ofa moving average smoothing function 902 of the scheduler smoothingfunction 302 of FIG. 3. Generally, the moving average smoothing function902 can be used to implement the scheduler smoothing function 302. Thefunctional block diagram can include a smoothing functional circuit.Note that although this diagram is in circuit form, it can beimplemented in software, hardware, or a combination thereof as well.

In at least one embodiment, a moving average of recent writes can beused to adjust the current recycle ratio 802. In such cases, the movingaverage of the recent writes can be sampled from a flash write operationqueue or the memory write operation queue 310.

The memory write operation queue 310 can include one or more writecommands, including the host writes 314 and/or the recycle writes 312.The host writes 314 and the recycle writes 312 within the memory writeoperation queue 310 can be recent write operations.

The recent write operations can be given weighting factors or weights908 using multiplication modules 910. Based on the weights 908, themoving average smoothing function 902 can determine whether the hostwrites 314 or the recycle writes 312 should happen next. The movingaverage smoothing function 902 can also feed the decision into a recenthistory window so that it can influence the next decision. Outputs ofthe multiplication modules 910 can be fed to a summation module 912 tocalculate the current recycle ratio 802.

Functions or operations of the memory controller 104 of FIG. 1 asdescribed above can be implemented in hardware, software, or acombination thereof. The memory controller 104 can be implemented withthe control unit 202 of FIG. 2, the storage unit 204 of FIG. 2, thememory interface unit 206 of FIG. 2, the host interface unit 208 of FIG.2, or a combination thereof.

For example, the multiplication modules 910 can be implemented with thecontrol unit 202 to multiply the recent write operations, including therecycle writes 312 and the host writes 314, and the weights 908. Alsofor example, the summation module 912 can be implemented with thecontrol unit 202 to calculate the current recycle ratio 802 based on theoutputs or results of the multiplication modules 910. The multiplicationmodules 910 can be coupled to the summation module 912 and the memorywrite operation queue 310.

The storage control system 100 of FIG. 1 is described with modulefunctions or order as an example. The modules can be partitioneddifferently. For example, the multiplication modules 910 and thesummation module 912 can be combined. Each of the modules can operateindividually and independently of the other modules.

Furthermore, data generated in one module can be used by another modulewithout being directly coupled to each other. The multiplication modules910 and the summation module 912 can be implemented as hardwareaccelerators (not shown) within the control unit 202 or can beimplemented as hardware accelerators (not shown) in the memorycontroller 104 or outside of the memory controller 104.

Referring now to FIG. 10, therein is shown a functional block diagram ofan exponential moving average smoothing function 1002 of the schedulersmoothing function 302 of FIG. 3. Generally, the exponential movingaverage smoothing function 1002 can be used to implement the schedulersmoothing function 302. The functional block diagram can include asmoothing functional circuit. Note that although this diagram is incircuit form, it can be implemented in software, hardware, or acombination thereof as well.

A preferred method of tracking the current recycle ratio 802 using amoving average can include an exponential moving average because it canbe the easiest to compute. The exponential moving average can be theeasiest to compute because it can require only the current recycle ratio802, denoted as RR_(C)(n), not a buffer of previous decisions.

The exponential moving average can require no divisions, but instead,just or only a subtraction module 1004, a multiplication module 1006,and an addition module 1008 each time. In addition, the exponentialmoving average can behave well on fixed-point hardware. If all writesfor a chosen window size are given equal weights, the smoothing functioncan be a simple-moving average function that is similar to a batchsmoothing function, which will be subsequently described.

The functional block diagram depicts a decision module 1010, whichdetermines a decision, denoted as Δ(n), of whether the host writes 314of FIG. 3 or the recycle writes 312 of FIG. 3 should happen next. Thedecision module 1010 can provide the decision as an input to thesubtraction module 1004. The subtraction module 1004 can subtract thecurrent recycle ratio 802 from the decision. In FIG. 10, Δ(n) can have avalue of “0” or “1” when one of the host writes 314 or the recyclewrites 312, respectively, is to occur at time n.

A subtraction result from the subtraction module 1004 can be multipliedby an exponential average parameter or a weight 1012, denoted as α, bythe multiplication module 1006, a result of which can then be added tothe current recycle ratio 802 by the addition module 1008 to generate anupdated current recycle ratio 1014, denoted as RR_(C)(N+1). The updatedcurrent recycle ratio 1014 can be fed to a unit delay module 1016 todelay the updated current recycle ratio 1014 by a predetermined unit oftime to generate a value of the current recycle ratio 802 for subsequentprocessing.

The functional block diagram depicts an initialization module 1018. Theinitialization module 1018 configures the current recycle ratio 802(RR_(c)) for the scheduler smoothing function 302. For example, a goodstarting point is to set the current recycle ratio 802 to be equal tothe target recycle ratio 406 (RR_(t)) of FIG. 4.

In the drive, the target recycle ratio 406 can be calculated every timethe spare pool size 502 of FIG. 5 changes, and the current recycle ratio802 can be immediately set to a new ratio that is equal to the targetrecycle ratio 406 so the scheduler 308 of FIG. 3 can start recycling tothe new ratio. If the current recycle ratio 802 were not set to be equalto the target recycle ratio 406 when the target recycle ratio 406 movedor changed and if there was a gap between the current recycle ratio 802and the target recycle ratio 406, we could end up with a burst of onlythe host writes 314 or the recycle writes 312 getting serviced.

Functions or operations of the memory controller 104 of FIG. 1 asdescribed above can be implemented in hardware, software, or acombination thereof. The memory controller 104 can be implemented withthe control unit 202 of FIG. 2, the storage unit 204 of FIG. 2, thememory interface unit 206 of FIG. 2, the host interface unit 208 of FIG.2, or a combination thereof.

For example, the subtraction module 1004 can be implemented with thecontrol unit 202 to subtract the current recycle ratio 802 from thedecision of whether the host writes 314 or the recycle writes 312 shouldhappen next. Also for example, the multiplication module 1006 can beimplemented with the control unit 202 to multiply the subtraction resultfrom the subtraction module 1004 by the weight 1012.

For example, the addition module 1008 can be implemented with thecontrol unit 202 to add the result of the multiplication module 1006 tothe current recycle ratio 802 to generate the updated current recycleratio 1014. Also for example, the decision module 1010 can beimplemented with the control unit 202 to determine the decision ofwhether the host writes 314 or the recycle writes 312 should happennext.

For example, the unit delay module 1016 can be implemented with thecontrol unit 202 to delay the updated current recycle ratio 1014 by thepredetermined unit of time to generate the value of the current recycleratio 802. Also for example, the initialization module 1018 can beimplemented with the control unit 202 to generate and supplyinitialization parameters for the target recycle ratio 406 of FIG. 4.

The subtraction module 1004 can be coupled to the multiplication module1006, the decision module 1010, and the initialization module 1018. Thedecision module 1010 can be coupled to the addition module 1008. Theaddition module 1008 can be coupled to the unit delay module 1016 andthe initialization module 1018.

The storage control system 100 of FIG. 1 is described with modulefunctions or order as an example. The modules can be partitioneddifferently. For example, the subtraction module 1004 and themultiplication module 1006 can be combined. Each of the modules canoperate individually and independently of the other modules.

Furthermore, data generated in one module can be used by another modulewithout being directly coupled to each other. The subtraction module1004, the multiplication module 1006, the addition module 1008, thedecision module 1010, the unit delay module 1016, and the initializationmodule 1018 can be implemented as hardware accelerators (not shown)within the control unit 202 or can be implemented as hardwareaccelerators (not shown) in the memory controller 104 or outside of thememory controller 104.

Referring now to FIG. 11, therein is shown a functional block diagram ofa batch smoothing function 1102 of the scheduler smoothing function 302of FIG. 3. Generally, the batch smoothing function 1102 can be used toimplement the scheduler smoothing function 302. The functional blockdiagram can include a smoothing functional circuit.

This type of smoothing function considers work in batches, using thetarget recycle ratio 406 of FIG. 4 to decide how many of the host writes314 and the recycle writes 312 to schedule for that batch. That is, atthe start of each batch, the smoothing function can create a schedule1104 of an order in which host and recycle work can occur for thatbatch.

For example, FIG. 11 depicts the storage control system 100 of FIG. 1having the target recycle ratio 406 of 0.75. At the start of each batch,the scheduler 308 can create the schedule 1104 with the host writes 314and the recycle writes 312, which the scheduler 308 plans to perform forthat batch.

The scheduler 308 can then work its way down the scheduler 308, pullingfrom an appropriate write queue for a host slot 1106 or a recycle slot1108, for which the scheduler 308 is currently processes. Theappropriate write queue can be the host write queue 304 or the recyclewrite queue 306. The scheduler 308 can pull the host writes 314 or therecycle writes 312 from the appropriate write queue for the host slot1106 or the recycle slot 1108, respectively.

The scheduler 308 can update the memory write operation queue 310 withan order by which the host writes 314 and the recycle writes 312 areexecuted. When a batch completes, the scheduler 308 can create a newschedule or another of the schedule 1104, if necessary.

With the batch smoothing function 1102, the scheduler 308 can stillchoose to deviate from the target recycle ratio 406 for periods of time,as indicated in FIG. 8. Thus, with the batch smoothing function 1102,there is still a feedback loop to ensure that a device or the memorycontroller 104 of FIG. 1 can be continually converging on the targetrecycle ratio 406.

It has been discovered that the memory sub-system 102 of FIG. 1including a solid-state drive (SSD) employing the scheduler smoothingfunction 302 for scheduling a mixture of the host writes 314 and therecycle writes 312 improves host performance. The host performance isimproved by maintaining steady host performance and consistent hostcommand latencies for providing even performance to the host system 108of FIG. 1.

It has also been discovered that the memory sub-system 102 including theSSD with the scheduler smoothing function 302 that utilizes the targetrecycle ratio 406 improves host performance. The host performance isimproved by using the target recycle ratio 406 to schedule the mixtureof the host writes 314 and the recycle writes 312 to maintain steadyhost performance and consistent host command latencies.

It has further been discovered that the memory sub-system 102 includingthe SSD with the scheduler smoothing function 302 that utilizes a targetwrite amplification to schedule a mixture of the host writes 314 and therecycle writes 312 improves host performance by providing steady hostperformance and consistent host command latencies.

It has further been discovered that the memory sub-system 102dynamically determining the recycle ratio 402 of FIG. 4 provides asteady state host performance and consistent host command latenciesthereby improving host performance.

It has further been discovered that the memory sub-system 102 adjustingthe recycle ratio 402 based on the spare pool size 502 of FIG. 5provides a steady state host performance and consistent host commandlatencies thereby improving host performance.

It has further been discovered that the scheduler smoothing function 302ceases servicing the host writes 314 only if the recycle ratio 402reaches one (1) or the spare pool size 502 becomes critically lowprovides improved reliability by servicing only the recycle writes 312to increase the spare pool size 502 to prevent device failure orextended inoperable responses.

It has further been discovered that the memory sub-system 102 includingthe SSD stops or ceases to perform recycle operations or the recyclewrites 312 altogether if the recycle ratio 402 becomes zero improveshost performance by servicing only the host writes 314 in response tothe larger spare pool.

It has further been discovered that the memory sub-system 102 includingthe SSD continues to perform the recycling operations in the backgroundat a low rate if the recycle ratio 402 becomes zero improves hostperformance by servicing more of the host writes 314 in response to thelarger spare pool.

It has further been discovered that the memory sub-system 102 optimizeshost performance by adjusting the recycle ratio 402 and the spare poolsize 502 to help even out host performance during workload transitionsor the transitional period 704 of FIG. 7.

It has further been discovered that the memory sub-system 102 includingthe SSD performing some of the recycle writes 312 when there are no hostoperations or the host writes 314 provides improved reliability. Theimproved reliability is provided because the recycle writes 312 increasethe spare pool size 502 thereby preventing device failure or extendedinoperable responses.

It has further been discovered that a solid-state drive (SSD) or thememory sub-system 102 that updates the target recycle ratio 406 based onhost and drive activity to update the scheduler smoothing function 302improves host performance by maintaining steady host performance andconsistent host command latencies. The target recycle ratio 406 isupdated based on the host and drive activity based on an appropriatemixture of the host writes 314 and the recycle writes 312.

It has further been discovered that the SSD or the memory sub-system 102with the scheduler smoothing function 302 that employs the smoothingfeedback loop improves host performance by maintaining steady hostperformance and consistent host command latencies. The host performanceis improved using the smoothing feedback loop to converge on the targetrecycle ratio 406.

It has further been discovered that the SSD or the memory sub-system 102with the scheduler smoothing function 302 that schedules a mixture byutilizing the moving average smoothing function 902 of FIG. 9 improveshost performance by maintaining steady host performance and consistenthost command latencies. The moving average smoothing function 902improves host performance using a moving average of recent schedulingactivity, including the host writes 314 and the recycle writes 312, andcomparing it to the target recycle ratio 406.

It has further been discovered that the SSD or the memory sub-system 102with the scheduler smoothing function 302 that allows the SSD to getahead on its maintenance/recycling work improves host performance bymaintaining steady host performance and consistent host commandlatencies. The SSD gets ahead on its maintenance/recycling work byscheduling extra cycles for the recycle writes 312 when the host system108 is not sending full of the host writes 314.

It has further been discovered that the SSD or the memory sub-system 102with the scheduler smoothing function 302 that allows the SSD to servicea burst of the host writes 314 improves host performance by maintainingsteady host performance and consistent host command latencies. The hostperformance is improved by the comparison module 804 of FIG. 8, the hostscheduler module 808 of FIG. 8, and the schedule host write module 812of FIG. 8 to provide a quick response to the host system 108 and catchup in the target recycle ratio 406 later.

It has further been discovered that the SSD or the memory sub-system 102with the scheduler smoothing function 302 that schedules a mixture ofthe host writes 314 and the recycle writes 312 improves host performanceby maintaining steady host performance and consistent host commandlatencies. The host performance is improved by choosing which types ofwrites to schedule, including the host writes 314 and the recycle writes312, in batches using the batch smoothing function 1102 in accordancewith the target recycle ratio 406.

The physical transformation of scheduling the recycle writes 312 and thehost writes 314 based on the recycle ratio 402 for writing to the memorydevices 110 of FIG. 1 results in movement in the physical world, such aspeople using the memory sub-system 102 based on the operation of thestorage control system 100. As the movement in the physical worldoccurs, the movement itself creates additional information that isconverted back in to receiving the recycle writes 312 from the recyclewrite queue 306 and receiving the host writes 314 from the host writequeue 304 for the continued operation of the storage control system 100and to continue the movement in the physical world.

Referring now to FIG. 12, therein is shown a flow chart of a method 1200of operation of a storage control system in a further embodiment of thepresent invention. The method 1200 includes: receiving a recycle writefrom a recycle write queue in a block 1202; receiving a host write froma host write queue in a block 1204; and scheduling the recycle write andthe host write for writing to a memory device in a block 1206.

Thus, it has been discovered that the storage control system of thepresent invention furnishes important and heretofore unknown andunavailable solutions, capabilities, and functional aspects for astorage control system with data management mechanism. The resultingmethod, process, apparatus, device, product, and/or system isstraightforward, cost-effective, uncomplicated, highly versatile,accurate, sensitive, and effective, and can be implemented by adaptingknown components for ready, efficient, and economical manufacturing,application, and utilization.

Another important aspect of the present invention is that it valuablysupports and services the historical trend of reducing costs,simplifying systems, and increasing performance.

These and other valuable aspects of the present invention consequentlyfurther the state of the technology to at least the next level.

While the invention has been described in conjunction with a specificbest mode, it is to be understood that many alternatives, modifications,and variations will be apparent to those skilled in the art in light ofthe aforegoing description. Accordingly, it is intended to embrace allsuch alternatives, modifications, and variations that fall within thescope of the included claims. All matters hithertofore set forth hereinor shown in the accompanying drawings are to be interpreted in anillustrative and non-limiting sense.

What is claimed is:
 1. A method of operation of a storage control systemfor a memory device comprising: receiving at least one recycle writefrom a recycle write queue; receiving at least one host write from ahost write queue; identifying a target recycle ratio in accordance witha current size of a spare pool of erased non-volatile memory blocksavailable to be written to, wherein the target recycle ratio is atargeted ratio of recycling page writes to host page writes; placing theat least one recycle write and the at least one host write in a writeoperation queue in accordance with the target recycle ratio; dispatchingthe at least one recycle write and the at least one host write from thewrite operation queue for writing data to the memory device; duringoperation of the storage control system, updating the target recycleratio in accordance with a change in the current size of the spare pool;and after updating the target recycle ratio: placing one or more recyclewrites and one or more host writes in the write operation queue inaccordance with the updated target recycle ratio; and dispatching theone or more recycle writes and the one or more host writes from thewrite operation queue for writing data to the memory device.
 2. Themethod as claimed in claim 1 wherein updating the target recycle ratioin accordance with a change in the current size of the spare poolcomprises increasing the target recycle ratio in accordance with adecrease in size of the spare pool or decreasing the target recycleratio in accordance with an increase in size of the spare pool.
 3. Themethod as claimed in claim 1, wherein identifying a target recycle ratioincludes the storage control system dynamically determining a firststeady-state recycle ratio in a first steady state of the storagecontrol system with respect to number of recycle write operations thatare performed per host page write operation; and wherein updating thetarget recycle ratio in accordance with a change in the current size ofthe spare pool includes detecting a change in the current size of thespare pool that satisfies predefined criteria, and the storage controlsystem, in response to detecting the change in the current size of thespare pool that satisfies the predefined criteria, updating the targetrecycle ratio to a second steady-state recycle ratio in a second steadystate of the storage control system with respect to number of recyclewrite operations that are performed per host page write operation,wherein the second steady-state recycle ratio is different from thefirst steady-state recycle ratio.
 4. The method as claimed in claim 1wherein identifying a target recycle ratio includes identifying thetarget recycle ratio based on an exponential moving average smoothingfunction by tracking a current recycle ratio.
 5. The method as claimedin claim 1 wherein identifying a target recycle ratio includesidentifying the target recycle ratio based on a smoothing feedback loopthat compares a current recycle ratio to a target recycle ratio.
 6. Themethod as claimed in claim 1 wherein identifying a target recycle ratioincludes identifying the target recycle ratio based on a recycle ratioas a function of a reciprocal of a write amplification.
 7. The method asclaimed in claim 1 wherein identifying a target recycle ratio includesidentifying the target recycle ratio based on a smoothing feedback loopwhen the at least one host write is not scheduled and a current recycleratio is greater than the target recycle ratio.
 8. A storage controlsystem for controlling operation of a non-volatile memory device coupledto the storage control system, the storage control system comprising: arecycle write queue for providing at least one recycle write; a hostwrite queue for providing at least one host write; and a memorycontroller coupled to the memory device, the memory controller havingone or more processors and including a scheduler module, coupled to therecycle write queue and the host write queue, for: identifying a targetrecycle ratio in accordance with a current size of a spare pool oferased non-volatile memory blocks available to be written to, whereinthe target recycle ratio is a targeted ratio of recycling page writes tohost page writes; placing the at least one recycle write and the atleast one host write in a write operation queue in accordance with thetarget recycle ratio; dispatching the at least one recycle write and theat least one host write from the write operation queue for writing datato the non-volatile memory device coupled to the storage control system;during operation of the storage control system, updating the targetrecycle ratio in accordance with a change in the current size of thespare pool; and after updating the target recycle ratio: placing one ormore recycle writes and one or more host writes in the write operationqueue in accordance with the updated target recycle ratio; anddispatching the one or more recycle writes and the one or more hostwrites from the write operation queue for writing data to the memorydevice.
 9. The system as claimed in claim 8 wherein the scheduler moduleis for increasing the target recycle ratio in accordance with a decreasein size of the spare pool or decreasing the target recycle ratio inaccordance with an increase in size of the spare pool.
 10. The system asclaimed in claim 8 wherein the scheduler module is for dynamicallydetermining a first steady-state recycle ratio in a first steady stateof the storage control system with respect to number of recycle writeoperations that are performed per host page write operation; and whereinthe scheduler module is also for detecting a change in the current sizeof the spare pool that satisfies predefined criteria, and in response todetecting the change in the current size of the spare pool thatsatisfies the predefined criteria, updating the target recycle ratio toa second steady-state recycle ratio in a second steady state of thestorage control system with respect to number of recycle writeoperations that are performed per host page write operation, wherein thesecond steady-state recycle ratio is different from the firststeady-state recycle ratio.
 11. The system as claimed in claim 8 whereinthe scheduler is for identifying the target recycle ratio based on anexponential moving average smoothing function by tracking a currentrecycle ratio.
 12. The system as claimed in claim 8 wherein thescheduler is for identifying the target recycle ratio based on asmoothing feedback loop that compares a current recycle ratio to atarget recycle ratio.
 13. The system as claimed in claim 8 wherein thescheduler is for identifying the target recycle ratio based on a recycleratio as a function of a reciprocal of a write amplification.
 14. Thesystem as claimed in claim 8 wherein the scheduler is for identifyingthe target recycle ratio based on an exponential moving averagesmoothing function by tracking a current recycle ratio with asubtraction module, a multiplication module, and an addition module. 15.The system as claimed in claim 8 wherein the scheduler is foridentifying the target recycle ratio based on a smoothing feedback loopwhen the at least one host write is not scheduled and a current recycleratio is greater than the target recycle ratio.